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400 msps 14-bit, 1.8 v cmos direct digital synthesizer ad9952 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2009 analog devices, inc. all rights reserved. features 400 msps internal clock speed integrated 14-bit dac 32-bit tuning word phase noise ?120 dbc/hz @ 1 khz offset (dac output) excellent dynamic performance >80 db sfdr @ 160 mhz (100 khz offset) a out serial i/o control 1.8 v power supply software and hardware controlled power-down 48-lead tqfp_ep package support for 5 v input levels on most digital inputs pll refclk multiplier (4 to 20) internal oscillator, can be driven by a single crystal phase modulation capability multichip synchronization high speed comparator (200 mhz toggle rate) applications agile lo frequency synthesis programmable clock generators test and measurement equipment acousto-optic device drivers general description the ad9952 is a direct digital synthesizer (dds) featuring a 14-bit dac (digital-to-analog converter) and operating up to 400 msps. the ad9952 uses advanced dds technology, coupled with an internal high speed, high performance dac to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 200 mhz. the ad9952 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word). the frequency tuning and control words are loaded into the ad9952 via a serial i/o port. the ad9952 is specified to operate over the extended industrial temperature range of ?40c to +105c. functional block diagram cos(x) control registers oscillator/buffer sync enable i/o update dac_r set dds core phase offset phase accumulator z ?1 z ?1 iout iout osk pwrdwnctl refclk refclk crystal out i/o port dds clock frequency tuning word clear phase accumulator amplitude scale factor dac system clock system clock sync_in sync_clk reset timing and control logic 4 to 20 clock multiplier 4 ad9952 32 32 14 14 19 14 0 m u x m u x comparator comp_out comp_in comp_in 03358-001 figure 1.
ad9952 rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 fun ctional block diagram .............................................................. 1 electrical specifications ................................................................... 3 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 equivalent input/output c ircuits ................................................ 12 theory of operation ...................................................................... 13 component blocks ..................................................................... 13 control register bit descriptions ............................................ 16 other register descriptions ..................................................... 18 modes of operation ................................................................... 18 programming features .............................................................. 18 synchronizing multiple ad9952s ............................................ 20 serial port operation ................................................................. 20 power - down functions ............................................................. 23 layout considerations ................................................................... 25 suggested application circuits ..................................................... 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 5 /09 rev. a to rev. b changes to comparator input characteristics, hysteresis parameter, table 1 .......................................................... 4 changes to pin configuration and function descriptions section and table 3 ........................................................................... 7 changes to table 5 .......................................................................... 15 changes to serial interface p ort pin description section ........ 22 changes to figure 32 ...................................................................... 26 added exposed pad notation to outline dimensions ............. 27 changes to ordering guide .......................................................... 27 5 /06 rev. 0 to rev. a updated format .................................................................. universal changes to electrical specifications section ................................ 3 changes to figure 3 .......................................................................... 9 chan ges to serial port operation section ................................... 20 inserted figure 24 , figure 25, and figure 26 .............................. 21 12/03 revision 0: initial version
ad9952 rev. b | page 3 of 28 electrical specifica tions av dd , dv dd = 1.8 v 5%, dv dd _i/o = 3.3 v 5%, dac_ r set = 3.92 k ? , externa l reference clock frequency = 40 0 mhz with refclk multiplier disabled, unless otherwise noted. dac output must be referenced to avdd, not agnd. table 1 . parameter temp min typ max unit ref clock input characteristics frequency range refclk multiplie r disabled f ull 1 400 mhz refclk multiplier enabled @ 4 f ull 20 100 mhz refclk multiplier enabled @ 20 f ull 4 20 mhz input capacitance 25c 3 pf input impedance 25c 1.5 k ? duty cycle 25c 50 % duty cycle with refclk multiplier enabled 25c 35 65 % refclk input power 1 f ull C 15 0 +3 dbm dac output characteristics resolution 14 bits full - scale output current 25c 5 10 15 ma gain error 25c C 10 +10 %fs out put offset 25c 0.6 a differential nonlinearity 25c 1 lsb integral nonlinearity 25c 2 lsb output capacitance 25c 5 pf residual phase noise @ 1 khz offset, 40 mhz a out refclk multiplier enabled @ 20 25c C 105 dbc/hz refclk multipli er enabled @ 4 25c C 115 dbc/hz refclk multiplier disabled 25c C 132 dbc/hz voltage compliance range 25c avdd ? 0.5 avdd + 0.5 v wideband spurious - free dynamic range ( sfdr ) 1 mhz to 10 mhz analog out 25c 73 dbc 10 mhz to 40 mhz analog out 25c 67 dbc 40 mhz to 80 mhz analog out 25c 62 dbc 80 mhz to 120 mhz analog out 25c 58 dbc 120 mhz to 1 60 mhz analog out 25c 52 dbc narrow - band sfdr 40 mhz analog out (1 mhz) 25c 87 dbc 40 mhz analog out (250 khz) 25c 89 dbc 40 mhz analog out (50 khz) 25c 91 dbc 40 mhz analog out (10 khz) 25c 93 dbc 80 mhz analog out (1 mhz) 25c 85 dbc 80 mhz analog out (250 khz) 25c 87 dbc 80 mhz analog out (50 khz) 25c 89 dbc 80 mhz analog out (10 khz) 25c 91 dbc 120 mhz analog out (1 mhz) 25c 83 dbc 120 mhz analog out (250 khz) 25c 85 dbc 120 mhz analog out (50 khz) 25c 87 dbc 120 mhz analog out (10 khz) 25c 89 dbc 160 mhz analog out (1 mhz) 25c 81 dbc 160 mhz analog out (250 khz) 25c 83 dbc 160 mhz analog out (50 khz) 25c 85 dbc 160 mhz analog out (10 khz) 25c 87 dbc
ad9952 rev. b | page 4 of 28 parameter temp min typ max unit comparator inpu t characteristics input capacitance 25c 3 pf input resistance 25c 500 k ? input current 25c 12 a hysteresis 25c 30 45 m v comparator output characteristics logic 1 voltage, high z load f ull 1.6 v logic 0 voltage, high z load f ull 0.4 v propagation delay 25c 3 ns output duty cycle error 25c 5 % ri se/fall time, 5 pf load 25c 1 ns toggle rate, high z load 25c 200 mhz output jitter 2 25c 1 ps rms comparator narrow - band sfdr 10 mhz ( 1 mhz) 25c 80 dbc 10 mhz ( 250 khz) 25c 85 dbc 10 mhz ( 50 khz) 25c 90 dbc 10 mhz ( 10 khz ) 25c 95 dbc 70 mhz ( 1 mhz) 25c 80 dbc 70 mhz ( 250 khz) 25c 85 dbc 70 mhz ( 50 khz) 25c 90 dbc 70 mhz ( 10 khz) 25c 95 dbc 110 mhz ( 1 mhz) 25c 80 dbc 110 mhz ( 250 khz) 25c 85 dbc 110 mhz ( 50 khz) 25c 90 dbc 110 mhz ( 1 0 khz) 25c 95 dbc 140 mhz ( 1 mhz) 25c 80 dbc 140 mhz ( 250 khz) 25c 85 dbc 140 mhz ( 50 khz) 25c 90 dbc 140 mhz ( 10 khz) 25c 95 dbc 160 mhz ( 1 mhz) 25c 80 dbc 160 mhz ( 250 khz) 25c 85 dbc 160 mhz ( 50 khz) 25c 90 dbc 160 mhz ( 10 khz) 25c 95 dbc clock generator output jitter 3 5 mhz a out 25c 100 ps rms 10 mhz a out 25c 60 ps rms 40 mhz a out 25c 50 ps rms 80 mhz a out 25c 50 ps rms 120 mhz a out 25c 50 ps rms 140 mhz a out 25c 50 ps rms 160 mh z a out 25c 50 ps rms timing characteristics serial control bus maximum frequency 4 f ull 25 mbps minimum clock pulse width low f ull 7 ns minimum clock pulse width high f ull 7 ns maximum clock rise/fall time f ull 2 ns minimum data setup time dvdd_i/o = 3.3 v 5 (tcsu, tdsu) f ull 3 ns minimum data setup time dvdd_i/o = 1.8 v 5 (tcsu, tdsu) f ull 5 ns minimum data hold time (tdh) f ull 0 ns maximum data valid time (tdv) f ull 25 ns
ad9952 rev. b | page 5 of 28 parameter temp min typ max unit wake - up time 6 full 1 ms minimum reset pulse width high full 5 sysclk c ycles 7 i/o update to sync_clk setup time dvdd_i/o = 3.3 v full 4 ns i/o update to sync_clk setup time dvdd_i/o = 3.3 v full 6 ns i/o update, sync_clk hold time full 0 ns latency i/o up date to frequency change prop agation delay 25c 24 sysclk c ycles i/o update to phase offset change prop agation delay 25c 24 sysclk c ycles i/o update to amplitude change prop agation delay 25c 16 sysclk c ycles cmos logic inputs logic 1 volta ge @ dvdd_i/o (pin 43) = 1.8 v 25c 1.25 v logic 0 voltage @ dvdd_i/o (pin 43) = 1.8 v 25c 0.6 v logic 1 voltage @ dvdd_i/o (pin 43) = 3.3 v 25c 2.2 v logic 0 voltage @ dvdd_i/o (pin 43) = 3.3 v 25c 0.8 v logic 1 current 25c 3 12 a logic 0 current 25c 12 a input capacitance 25c 2 pf cmos logic outputs (1 ma load) dvdd_i/o = 1.8 v logic 1 voltage 25c 1.35 v logic 0 voltage 25c 0.4 v cmos logic outputs (1 ma load) dvdd_i/o = 3.3 v logic 1 voltage 25c 2.8 v l ogic 0 voltage 25c 0.4 v power consumption (avdd = dvdd = 1.8 v) single - tone mode 25c 162 171 mw rapid power - down mode 25c 150 160 mw full - sleep mode 25c 20 27 mw synchronization function 8 maximum sync clock rate (dvdd_i/o = 1.8 v ) 25c 62.5 mhz maximum sync clock rate (dvdd_i/o = 3.3 v) 25c 100 mhz sync_clk alignment resolution 9 25c 1 sysclk c ycles 1 to achieve the best possible phase noise, the largest amplitude clock possible should be used. reducing the clock input ampli tude reduces the phase noise pe r forman ce of the device. 2 represents the cycle - to - cycle residual jitter from the comparator alone. 3 represents the cycle - to - cycle residual jitter from the dds core driving the comparator. 4 the maxim um frequency of the serial i/o p ort refers to the maximum spee d of the port during a write operation. during a register readback, the maximum port speed is restricted to 2 mb ps . 5 setup time refers to the tcsu (setup time of the falling edge of cs to the sclk rising edge) and tdsu (setup time of th e data change on sdio to the sclk rising edge) . 6 wake - up time refers to the recovery from analog power - down modes (see the power - down functions section). the longest time required is for the refe r ence clock multiplier pll to reloc k to the reference. the wake - up time assumes there is no capacitor on dacbp and that the recommended pll loop filter values are used. 7 sysclk cycle refers to the actual clock frequency used on - chip by the dds. if the reference clock multiplier is used to multiply the external reference clock frequency, the sysclk frequency is the external frequency multiplied by the reference clock multiplication factor. if the reference cloc k multiplier is not used, the sysclk fr e quency is the same as the external refere nce clock frequency. 8 sync_clk = ? sysclk rate. for sync_clk rates 50 mhz, the high speed sync enable bit, cfr2 [11], should be set. 9 this parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between s ystem clock rising edges. if the system clock edges are aligned, the synchronization function should not increase the skew between the two edges.
ad9952 rev. b | page 6 of 28 absolute maximum rat ings table 2 . parameter rating maximum junction temperature 150c dvdd_i /o 4 v avdd, dvdd 2 v digital input voltage (dvdd_i/o = 3.3 v) C 0.7 v to +5.25 v digital input voltage (dvdd_i/o = 1.8 v) C 0.7 v to +2.2 v digital output current 5 ma storage temperature range C 65c to +150c operating temperature range C 40c to +105 c lead temperature (10 sec soldering) 300c ja 38c/w jc 15c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the op erational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 400 0 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. t herefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9952 rev. b | page 7 of 28 pin configuration and function descrip tions scl k s d i o s d o c s 3 4 8 9 1 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 7 6 2 5 10 11 12 25 26 27 3 7 41 42 43 44 45 46 47 48 dacb p agn d iou t iou t avd d agn d avd d avd d avd d agn d agn d agn d agn d a v d d avd d avd d comp_ou t c omp _ i n c omp _ i n dgn d dgn d dvd d p w rdwnct l re s e t io sy n c dvdd_i/ o sync_i n s y nc_cl k os k dgnd dgn d i/o updat e dvd d dgn d avd d agn d a v d d agn d re f c l k re f c l k cr y stal ou t clkmodesel e c t loop _ fi l te r a d 9 9 5 2 to p view (not t o scal e ) 40 39 38 dac_ r se t 13 14 15 16 17 18 19 20 21 22 23 24 03358-002 figure 2. pin configuration note that the exposed paddle on the bottom of the package is a ground connection for the dac and must be attached to agnd in any board layout. note that pin 43, dvdd_i/o, can be powered to 1.8 v or 3.3 v; however, the dvdd pins (pin 2 and pin 34) can only be powered to 1.8 v. table 3 . 48 - lead tqfp/ep pin no. mnemonic i/o description 1 i/o update i the rising edge transfers the contents of the internal buffer memory to the i/o registers. this pin must be set up and held around the sync_clk output signal. 2, 34 dvdd i digit al power supply pins (1.8 v). 3, 33, 42 , 47, 48 dgnd i digital power ground pins. 4, 6, 13, 16, 18, 19, 25, 27, 29 avdd i analog power supply pins (1.8 v). 5, 7, 14, 15, 17, 22, 26, 32 agnd i analog power ground pins. 8 refclk i com plementary reference clock/oscillator input. when the refclk port is operated in single - ended mode, refclk should be decoupled to avdd with a 0.1 f capacitor. 9 refclk i reference clock/oscillator input. see the clock input section for details on the oscillator /refclk operation. 10 crystal out o output of the oscillator section. 11 clkmodeselect i control pin for the oscillator section. when high, the oscillator section is enabled. when low, the oscillator section is bypassed. 12 loop_filter i this pin provides the connection for the external zero compensation network of the refclk multipliers pll loop filter. the network consists of a 1 k ? resistor in series with a 0.1 f capacitor tied to avdd. 20 iout o complementary dac output. should be biased through a resistor to avdd, not agnd. 21 iout o dac output. should be biased through a resistor to avdd, not agnd.
ad9952 rev. b | page 8 of 28 pin no. mnemonic i/o description 23 dacbp i dac biasline decoupling pin. a 0.1 f capacitor to agnd is recomm ended. 24 dac_r set i a resistor (3.92 k ? nominal) connected from agnd to dac_r set establishes the reference current for the dac. 28 comp_out o comparator output. 30 comp_in i comparator input. 31 comp_in i comparator complementary inp ut . 35 pwrdwnctl i input pin used as an external power - down control. s ee table 7 for additional information. 36 reset i active high hardware reset pin. assertion of the reset pin forces the ad9952 to the initial state, as describ ed in the i/o port register map (see table 5 ) . 37 iosync i asynchronous active high reset of the serial port controller. when high, the current i/o operation is immediately terminated , enabling a new i/o operation to commence on ce iosync is returned low. if unused, ground this pin ; do not allow this pin to float. 38 sdo o when operating the i/o port as a 3 - wire serial port, this pin serves as the serial data output. when operated as a 2 - wire serial port, this pin is unused and c an be left unconnected. 39 cs i this pin functions as an active low chip select that allows multiple devices to share the i/o bus. 40 sclk i this pin functions as the serial data clock for i/o operations. 41 sdio i/o when operating the i/o port as a 3 - wire serial port, this pin serves as the serial data input only. when operated as a 2 - wire serial port, this pin is the bidirectional serial data pin. 43 dvdd_i/o i digital power supply . for i/o cells only, 3.3 v. 44 sync_in i input s ign al u sed to s ynchronize m ultiple ad9952 s. this input is connected to the sync_clk output of a master ad9952 . 45 sync_clk o clock o utput p in t hat s erves as a s ynchronizer for e xternal h ardware. 46 osk i input p in u sed to c ontrol the d irection of t he s haped o n - o ff k eying f unction when p rogrammed f or o peration. osk is synchronous to the sync_clk pin. when osk is not programmed, this pin should be tied to dgnd. paddle exposed paddle i the exposed paddle on the bottom of the package is a ground connection for the dac and must be attached to agnd in any board layout. note that pin 43, dvdd_i/o, can be powered to 1.8 v or 3.3 v; however, the dvdd pins (pin 2 and pin 34) can only be powered to 1.8 v.
ad9952 rev. b | page 9 of 28 typical performance characteris tics center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz sp an 200mhz sweep 55. 56 s (401 pts) w1 s2 s3 fc aa ref 0dbm peak log 10db/ a tten 10db mkr1 98.0mhz ?70.68db 1 1r marker 100.000000mhz ?70.68db 03358-003 figure 3. f out = 1 mhz fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ? 90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz sp an 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm peak log 10db/ a tten 10db mkr1 80.0mhz ? 69.12db 1 1r marker 80.000000mhz ? 69.12db 03358-004 figure 4. f out = 10 mhz, fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz sp an 200mhz sweep 55. 56 s (401 pts) w1 s2 s3 fc aa ref 0dbm peak log 10db/ a tten 10db mkr1 0hz ?68.44db 1 1r marker 40.000000mhz ?68.44db 03358-005 figure 5. f out = 40 mhz, fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz sp an 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm peak log 10db/ a tten 10db mkr1 80.0mhz ?61.55db 1 1r marker 80.000000mhz ?61.55db 03358-006 figure 6. f out = 80 mhz fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 v bw 3khz sp an 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm peak log 10db/ a tten 10db mkr1 40.0mhz ?56.2db 1 1r marker 40.000000mhz ?56.2db 03358-007 figure 7. f out = 120 mhz, fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz sp an 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm peak log 10db/ a tten 10db mkr1 0hz ?53.17db 1 1r marker 80.000000mhz ?53.17db 03358-008 figure 8. f out = 160 mhz, fclk = 400 msps, wbsfdr
ad9952 rev. b | page 10 of 28 center 1.105mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz sp an 2mhz swee p 199.2 s (401 pts) w1 s2 s3 fc aa st ref ?4dbm peak log 10db/ a tten 10db mkr1 1.105mhz ?5.679dbm 1 marker 1.105000mhz ?5.679dbm 03358-009 figure 9. f out = 1.1 mhz, fclk = 400 msps, nbsfd r, 1 mhz center 10mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz sp an 2mhz swee p 199.2 s (401 pts) w1 s2 s3 fc aa ref 0dbm peak log 10db/ a tten 10db mkr1 85khz ?93.01db 1 1r marker 40.000000mhz ?56.2db 03358-010 figure 10 . f out = 10 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 39.9mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz sp an 2mhz swee p 199.2 s (401 pts) w1 s2 s3 fc aa ref 0dbm peak log 10db/ a tten 10db mkr1 39.905mhz ?5.347dbm 1 marker 39.905000mhz ?5.347dbm 03358-0 1 1 figure 11 . f out = 39.9 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 80.25mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz sp an 2mhz swee p 199.2 s (401 pts) w1 s2 s3 fc aa st ref ?4dbm peak log 10db/ a tten 10db mkr1 80.301mhz ?6.318dbm 1 marker 80.301000mhz ?6.318dbm 03358-012 figure 12 . f out = 80.3 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 120.2mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz sp an 2mhz swee p 199.2 s (401 pts) w1 s2 s3 fc aa st ref ?4dbm peak log 10db/ a tten 10db mkr1 120.205mhz ?6.825dbm 1 marker 120.205000mhz ?6.825dbm 03358-013 figure 13 . f out = 120.2 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 160.5mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz sp an 2mhz swee p 199.2 s (401 pts) w1 s2 s3 fc aa st ref ?4dbm peak log 10db/ a tten 10db mkr1 600khz ?0.9 1 1db 1 center 160.5000000mhz 03358-014 figure 14 . f out = 160 mhz, fclk = 400 msps, nbsfdr, 1 mhz
ad9953 rev. a | page 11 of 32 figure 16. residual phase noise with f out = 159.5 mhz, f clk = 400 msps (green), 4 100 msps (red), and 20 20 msps (blue) ch1 200mv ? 1 it 4.0ps/pt 3.1ns m 200ps 20.0gs/s a ch1 708mv 03374-0-031 t 1 = 3.156ns t 2 = 3.04ns ? t = ?116.0ps 1/ ? t = ?8.621ghz figure 17. residual peak-to-peak jitter of dds and comparator operating together at 160 mhz figure 18. residual phase noise with f out = 9.5 mhz, f clk = 400 msps (green), 4 100 msps (red), and 20 20 msps (blue) ref2 200mv 500ns r2 r1 it 10.0ps/pt ?100ps m 500ps 20.0gs/s a ch1 708mv 03374-0-030 fall (r1) = 396.4ps rise(r2) = 464.3ps figure 19. comparator rise and fall time at 160 mhz
ad9952 rev. b | page 12 of 28 equivalent input/out put c ircuit s input dvdd_i/o avoid overdriving digital inputs. forward-biasing esd diodes may couple digital noise onto power pins. digital inputs 03358-019 figure 19 . digital inputs iout iout must terminate outputs to avdd for current flow. do not exceed the output voltage compliance rating. digital outputs 03358-020 figure 20 . dac outputs comparator inputs comp_in comp_in 03358-021 figure 21 . comparator inputs avdd comparator output 03358-022 figure 22 . comparator outputs
ad9952 rev. b | page 13 of 28 theory of operation component blocks dds core the output frequency ( f o ) of the dds is a function of the frequency of the system clock (sysclk), the value of the frequency tuning word ( ftw ), and the capacity of the accum u lator (2 32 , in this case). the exact relationship is given below with f s defined as the frequency of sysclk. ( ) ( ) 31 32 2 0 2 / = ftw with f ftw f s o ( ) ( ) 1 C 2 2 2 / C 1 32 31 32 < < = ftw with ftw f f s o the value at the output of the phase accumulator is translated to an amplitude value via the cos(x) functional block and routed to the da c. to introduce a phase offset, the p hase o ffset word, or pow , is used. the actual phase offset , f for the output of the dds core , is determined by the following relationship: 14 2 360 pow = in certain applications , it is desirable to force the ou tput signal to zero phase. s etting the ftw or pow to 0 does not accomplish this; it only results in the dds core holdi ng its current phase value or continuing to run at the current phase, respectively. to set the phase offset to zero , a control bit is requ ired to force the phase accum u lator output to zero. the bits to clear the pha se accumulator are found in control function re gister 1 , bit [13] and bit [8]. at power - up, the clear phase accumulator bit is set to logic 1, but the buffer memory for this bit is cleared (logic 0). ther e fore, upon power - up, the phase accumulator remain s clear until the first i/o update is issued. phase - locked loop (pll) the pll allows multiplication of the refclk frequency. co n trol of the pll is accomplished by programming the 5 - bit refclk multiplier portion of control function re g ister 2 (cfr2) , bits [ 7:3 ] . when programmed for values ranging from 0x04 to 0x14 (4 decimal to 20 decimal), the pll multiplies the refclk input fr e quency by the corresponding decimal value. however, th e maximum ou t put frequency of the pll is restricted to 400 mhz. whenever the pll value is changed, the user should be aware that time must be allocated to allow the pll to lock (a p proximately 1 ms). the pll is bypassed by programming a value outside the ra nge of 4 ( decimal ) to 20 (decimal). when bypassed, the pll is shut down to co n serve power. clock input the ad9952 supports various clock methodologies. support for differential or single - ended input clocks and enabling of an on - chip oscillator and/or a pl l multip lier is all controlled via user - programmable bits. the ad9952 can be configured in one of six operating modes to generate the system clock. the modes are configured using the clkmod e select pin, control function register 1 ( cfr1 ) [ 4 ] , and cfr2 [ 7:3 ] . connect the clkmodeselect exte r nal pin to l ogic h igh to enable the on - chip crystal oscillator circuit. with the on - chip oscillator enabled, connect an external crystal to the refclk and refclkb inputs to produce a low frequency reference clock in the ran ge of 20 mhz to 30 mhz. the signal generated by the o s cillator is buffered before it is delivered to the rest of the chip. this buffered signal is available via the crystal out pin. cfr1 [ 4 ] can be used to enable or disable the buffer, turning on or turnin g off the system clock. the oscillator itself is not powered down to avoid long start - up times associated with tur n ing on a crystal oscillator. writing cfr2 [ 9 ] to l ogic h igh enables the cry s tal oscillator output buffer. logic low at cfr2 [ 9] disables the oscillator output buffer. connecting clkmodeselect to l ogic l ow disables the on - chip oscillator and the oscillator output buffer. with the oscill a tor disabled, an external oscillator must provide the refclk and/or refclkb signals. for differential operatio n, these pins are driven with complementary signals. for single - ended operation, a 0.1 f capacitor should be connected between the u n used pin and the analog power supply. with the capacitor in place, the clock input pin bias voltage is 1.35 v. in addition , the pll can be used to multiply the reference frequency by an integer value in the range of 4 ( decimal ) to 20 ( decimal ) . table 4 summarizes the clock modes of operation. note that the pll multip lier is controlled via cfr2 [7:3] , indepen d ent of cfr1 [ 4 ] .
ad9952 rev. b | page 14 of 28 table 4 . clock input modes of operation cfr1 [ 4 ] clkmodeselect cfr2 [ 7:3 ] oscillator enabled system clock frequency range (mhz) low high 3 < m < 21 yes f clk = f osc m 80 < f clk < 400 low high m < 4 or m > 20 yes f clk = f osc 20 < f clk < 30 low low 3 < m < 21 no f clk = f osc m 80 < f clk < 400 low low m < 4 or m > 20 no f clk = f osc 10 < f clk < 400 high x x no f clk = 0 n/a dac output the ad9952 incorporates an integrated 14 - bit current output dac. unl ike most dacs, this output is referenced to avdd, not agnd. two complementary outputs provide a combined full - scale output current (i out ). differential outputs reduce the amount of common - mode noise that might be present at the dac output, o f fering the ad vantage of an increased signal - to - noise ratio. the full - scale current is controlled by an external resistor (r set ) connected b e tween the dac_r set pin and the dac ground (agnd_dac). the full - scale current is propo r tional to the resistor value as follows: out set i r / 19 . 39 = the maximum full - scale output current of the combined dac outputs is 15 ma, but limiting the output to 10 ma provides the best spurious - free dynamic range (sfdr) performance. the dac output compliance range is avdd + 0.5 v to avdd C 0 .5 v. voltages developed beyond this range cause excessive dac disto r tion and could potentially damage the dac output circuitry. proper attention should be paid to the load termination to keep the output voltage within this compl i ance range. comparator many applications require a square wave signal rather than a sine wave. for example, in most clocking applications a high slew rate helps to reduce phase noise and jitter. to support these applications, the ad9952 includes an on - chip compar a tor. the compar ator has a bandwidth greater than 200 mhz and a common - mode input range of 1.3 v to 1.8 v. by setting the comparator power - down bit, cfr1 [ 6 ] , the comparator can be turned off to save on power consumption. serial i / o port the ad9952 serial port is a flexi ble, synchronous serial commun i cations port that allows easy interface to many industry - standard microcontrollers and microprocessors. the serial i/o port is co m patible with most synchronous transfer formats, including both the motorola 6905/11 spi? and in tel? 8051 ssr protocols. the interface allows read/write access to all registers that co n figure the ad9952 . msb first or lsb first transfer formats are supported. t he ad9952 serial interface port can be configured as a single pin i/o (sdio) that allows a 2 - wire interface or two unidirectional pins for in/out (sdio/sdo), which in turn enable a 3 - wire inte r face. two optional pins, iosync and cs register map and descriptions , enable greater flexibility for system d e sign in the ad9952 . please see the serial port operation section for details on how to program the ad9952 through the s erial i/o port. the register map is listed in table 5 .
ad9952 rev. b | page 15 of 28 table 5 . register map register n ame (serial address) register address bit range (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 d efault value control function register 1 (cfr1) (0 x 00) [ 7:0 ] digital power - d own comparator power - down dac power - down clock input power - down external power - down mode not used sync_clk out disable not used 0 x 00 [ 15:8 ] not used not used auto clr phase accum . enable sine output not used clear phase accum. sdio input only lsb first 0 x 00 [ 23:16 ] automatic sync enable sof tware manual sync not used 0 x 00 [ 31:24 ] not used load arr @ i/o update osk enable auto osk keying 0 x 00 control function register 2 (cfr2) (0 x 01) [ 7:0 ] refclk multiplier 0 x 00 or 0 x 01, or 0 x 02 or 0 x 03: bypass multiplier 0 x 04 to 0 x 14: 4 to 20 multiplica tion vco range charge pump current [ 1:0 ] 0 x 00 [ 15:8 ] not used high speed sync enable hardware manual sync enable crystal out pin active not used 0 x 00 [ 23:16 ] not used 0x 18 amplitude scale factor (asf) (0 x 02) [ 7:0 ] amplitude scale factor register [ 7: 0 ] 0 x 00 [ 15:8 ] auto ramp rate speed contr o l [ 1:0 ] amplitude scale factor register [ 13:8 ] 0 x 00 amplitude ramp rate ( arr) (0 x 03) [ 7:0 ] amplitude ramp rate register [ 7:0 ] 0 x 00 frequency tuning word 0 (ftw0) (0 x 04) [ 7:0 ] frequency tuning word 0 [ 7:0 ] 0 x 00 [ 15:8 ] frequency tuning word 0 [ 15:8 ] 0 x 00 [ 23:16 ] frequency tuning word 0 [ 23:16 ] 0 x 00 [ 31:24 ] frequency tuning word 0 [ 31:24 ] 0 x 00 phase offset word (pow ) (0 x 05) [ 7:0 ] phase offset word 0 [ 7:0 ] 0 x 00 [ 15:8 ] not used [ 1:0 ] phase offset word 0 [ 13:8 ] 0 x 00
ad9952 rev. b | page 16 of 28 control register bit descriptions control function register 1 (cfr1) the cfr1 bits control the functions, features, and modes of the ad9952. the functionality of each bit is d e tailed below. cfr1 [ 31:27 ] : not used cfr1 [ 26] : amplitude ramp rate load control bit cfr1 [ 26 ] = 0 (default). the amplitude ramp rate timer is loaded only upon timeout (timer = 1) and is not loaded due to an i/o update input signal. cfr1 [ 26 ] = 1. the amplitude ramp rate timer i s loaded upon timeout (timer = 1) or at the time of an i/o update input sig nal. cfr1 [ 25] : shaped on - off keying enable bit cfr1 [ 25 ] = 0 (default). shaped on - off keying is b y passed. cfr1 [ 25 ] = 1. shaped on - off keying is enabled. when e nabled, cfr1 [ 24 ] controls the mode of operation for this f un c tion. cfr1 [ 24] : auto shaped on - off keying enable bit ( o nly v alid when cfr1 [ 25 ] i s a ctive h igh) cfr1 [ 24 ] = 0 (default). when cfr1 [ 25 ] is active, a logic 0 on cfr1 [ 24 ] enables the manual shaped on - off keying oper a tion. each amplitude sample sent to the dac is multiplied by the amplitude scale factor. see the shaped on - off keying se c tion for d etails. cfr1 [ 24 ] = 1. when cfr1 [ 25 ] is active, a logic 1 on cfr1 [ 24 ] enables the auto shaped on - off keying oper a tion. toggling the osk pin high cause s the output scalar to ramp up from zero scale to the amplitude scale factor at a rate dete r mined by the amplitude ramp rate. toggling the osk pin low cause s the output to ramp down from the amplitude scale factor to zero sca le at the amplitude ramp rate (s ee the shaped on - off keying s ection ). cfr1 [ 23] : automatic synchronization enable bit cfr1 [ 23 ] = 0 (default). the automatic synchronization fe a ture of multiple ad9952s is inactive. cfr1 [ 23 ] = 1. the automatic synchronization feature of multiple ad9952s is active. the device synchronize s its i n ternal synchronization clock (sync_clk) to align to the signal pr e sent on the sync_in input (s ee the synchronizing multiple ad9952 section ). cfr1 [ 22] : so ftware manual sync hronization of multiple ad9952s cfr1 [ 22 ] = 0 (default). the manual synchronization fe a ture is inactive. cfr1 [ 22 ] = 1. the software controlled manual synchroniz a tion feature is executed. the sync_clk rising edge is advanced by one sync_c lk cycle and this bit is cleared. to a d vance the rising edge multiple times, this bit nee ds to be set for each advance (s ee the synchronizing multiple ad9952 se c tion ). cfr1 [ 21:14 ] : not used cfr1 [13]: auto -c lear phase accumulator bit cfr1 [ 13 ] = 0 (default). the current state of the phase accumulator remains unchanged when the frequency tu n ing word is applied. cfr1 [ 13 ] = 1. this bit synchronously clears the phase accumulator automatically (by loadings 0s) for one cycle upon rece p tion of an i/o update signal. cfr1 [ 12] : sine/cosine select bit cfr1 [ 12 ] = 0 (default). the angle - to - amplitude conve r sion logic employs a cosine function. cfr1 [ 12 ] = 1. the angle - to - amplitude conversion logic em ploys a sine function. cfr1 [ 11] : not use d cfr1 [ 10] : clear phase accumulator cfr1 [ 10 ] = 0 (default). the phase accumulator fun c tions as normal. cfr1 [ 10 ] = 1. the phase accumulator memory elements are cleared and held clear until this bit is cleared. cfr1 [9] : sdio input only cfr1 [9] = 0 (defa ult). the sdio pin has bidirectional oper a tion (2 - wire serial programming mode). cfr1 [9] = 1. the serial data i/o pin (sdio) is confi g ured as an input only pin (3 - wire serial programming mode). cfr1 [8] : lsb first cfr1 [8] = 0 (default). msb first format is active. cfr1 [8] = 1. the serial inter face accepts serial data in lsb - first format. cfr1 [7] : digital power - down bit cfr1 [7] = 0 (default). all digital functions and clocks are a c tive. cfr1 [7] = 1. all non -i/ o digital functionality is su s pended, lowe ring the power significantly.
ad9952 rev. b | page 17 of 28 cfr1 [6] : comparator power - down bit cfr1 [6] = 0 (default). the comparator is enabled for oper a tion. cfr1 [6] = 1. the comparator is disabled and is in its lowest power dissipation state. cfr1 [5] : dac power - down bit cfr1 [5] = 0 (default). the dac is enabled for operation. cfr1 [5] = 1. the dac is disabled and is in its lowest power dissipation state. cfr1 [4] : clock input power - down bit cfr1 [4] = 0 (default). the clock input circuitry is e n abled for operation. cfr1 [4] = 1. the clock input circuitry is disabled and the de vice is in its lowest power dissipation state. cfr1 [3] : external power - down mode cfr1 [3] = 0 (default). selects the external rapid recovery power - down mode. in this mode, when the pwrdwnctl input pin i s high, the digital logic and the dac digital logic are powered down. the dac bias circuitry, pll, oscillator, and clock input circuitry are not po w ered down. cfr1 [3] = 1. selects the external full power - down mode. in this mode, when the pwrdwnctl input pin is high, all functions are powered down. this includes the dac and pll, which take a significant amount of time to power up. cfr1 [2] : not used cfr1 [1] : sync_clk disable bit cfr1 [1] = 0 (default). the sync_clk pin is active. cfr1 [1] = 1. the sync_cl k pin assumes a static logic 0 state to keep noise generated by the digital circuitry at a min i mum. however, the synchronization circuitry remains active (inte r nally) to maintain normal device timing. cfr1 [0] : not used, leave at 0 control function regist er 2 (cfr2) the cfr2 bits control the fun c tions, features, and modes of the ad9952, primarily related to the analog sections of the chip. cfr2 [ 23:12 ] : not used cfr2 [ 11] : high speed sync enable bit cfr2 [ 11 ] = 0 (default). the high speed sync enhanc e ment is off. cfr2 [ 11 ] = 1. the high speed sync enhancement is on. this bit should be set when us ing the auto synchronization feature for sync_clk inputs beyond 50 mhz, (200 msps sysclk). see the synchronizing multiple ad9952 s sectio n. cfr2 [ 10] : hardware manual sync enable bit c fr2 [ 10 ] = 0 (default). the hardware manual sync fun c tion is off. cfr2 [ 10 ] = 1. the hardware manual sync function is e nabled. while this bit is set, a rising edge on the sync_in pin cause s the device to advance the sync_clk rising edge by one refclk cycle. unlike the software manual sync enable bit, this bit does not self - clear. once the hardware manual sync mode is enabled, it stay s enab led until this bit is cleared ( s ee the synchroni zing multiple ad9952 section) . cfr2 [9] : crystal out enable bit cfr2 [9] = 0 (default) . t he crystal out pin is ina c tive. cfr2 [9] = 1. the crystal out pin is active. when a c tive, the crystal oscillator circuitry output drives the cry s tal out pin, which c an be connected to other devices to produce a reference frequency. the oscillator respond s to cry s tals in the range of 20 mhz to 30 mhz. cfr2 [8] : not used cfr2 [ 7:3 ] : reference clock multiplier control bits this 5 - bit word controls the multiplier value o ut of the clock - multiplier (pll) block. valid values are 4 decimal to 20 decimal (0x04 to 0x14). values entered outside this range bypass the clock multiplier. see the phase - locked loop (pll) section ). cfr2 [2] : vco range control b it this bit is used to control the range setting on the vco. cfr2 [2] = 0 (default). t he vco operates in a range of 100 mhz to 250 mhz. cfr2 [2] = 1. t he vco operates in a range of 250 mhz to mhz. cf r2 [ 1:0 ] : charge pump current control bits these b its are used to control the current setting on the charge pump. the default setting, cfr2 [1:0] , sets the charge pump current to the default value of 75 a. for each bit added ( bit 01, bit 10, and bit 11), 25 a of current is added to the charge pump current: 100 a, 125 a, and 150 a.
ad9952 rev. b | page 18 of 28 other register descriptions amplitude scale factor (asf) the asf register stores the 2-bit auto ramp rate speed value and the 14-bit amplitude scale factor used in the output shaped keying (osk) operation. in auto osk operation, asf [15:14] tell the osk block how many amplitude steps to take for each increment or decrement. asf [13:0] sets the maximum value for the osk internal multiplier. in manual osk mode, asf [15:14] have no effect. asf [13:0] provide the output scale factor directly. if the osk enable bit is cleared, cfr1 [25] = 0, this register has no effect on device operation. amplitude ramp rate (arr) the arr register stores the 8-bit amplitude ramp rate used in the auto osk mode. this register programs the rate at which the amplitude scale factor counter increments or decrements. if the osk is set to manual mode, or if osk enable is cleared, this register has no effect on device operation. frequency tuning word 0 (ftw0) the frequency tuning word is a 32-bit register that controls the rate of accumulation in the phase accumulator of the dds core. its specific role depends on the device mode of operation. phase offset word (pow) the phase offset word is a 14-bit register that stores a phase offset value. this offset value is added to the output of the phase accumulator to offset the current phase of the output signal. the exact value of phase offset is given by the following formula: ?? ? ? ? ? ? ? ?? 360 2 14 pow or 14 2 360 ? ? ? ? ? ? ? ? ? ? pow where ? is the desired phase offset, in degrees. modes of operation single-tone mode in single-tone mode, the dds core uses a single tuning word. whatever value is stored in ftw0 is supplied to the phase accumulator. this value can only be changed manually, which is done by writing a new value to ftw0 and by issuing an i/o update. phase adjustment is possible through the phase offset register. programming features phase offset control a 14-bit phase offset () can be added to the output of the phase accumulator by means of the control registers. this feature provides the user with two different methods of phase control. the first method is a static phase adjustment, where a fixed phase offset is loaded into the appropriate phase offset register and left unchanged. the result is that the output signal is offset by a constant angle relative to the nominal signal. this allows the user to phase align the dds output with some external signal, if necessary. in the second method of phase control, the user regularly updates the phase offset register via the i/o port. by properly modifying the phase offset as a function of time, the user can implement a phase modulated output signal. however, both the speed of the i/o port and the frequency of sysclk limit the rate at which phase modulation can be performed. the ad9952 allows for a programmable continuous zeroing of the phase accumulator as well as a clear and release or automatic zeroing function. each feature is individually controlled via the cfr1 bits. cfr1 [13] is the automatic clear phase accumulator bit. cfr1 [10] clears the phase accumulator and holds the value to 0. continuous clear bit the continuous clear bit is simply a static control signal that, when active high, holds the phase accumulator at 0 for the entire time the bit is active. when the bit goes low, inactive, the phase accumulator is allowed to operate. clear and release function when set, the auto-clear phase accumulator clears and releases the phase accumulator upon receiving an i/o update. the automatic clearing function is repeated for every subsequent i/o update until the appropriate auto-clear control bit is cleared. shaped on-off keying the shaped on-off keying function of the ad9952 allows the user to control the ramp-up and ramp-down time of an on-off emission from the dac. this function is used in burst transmissions of digital data to reduce the adverse spectral impact of short, abrupt bursts of data. auto and manual shaped on-off keying modes are supported. the auto mode generates a linear scale factor at a rate determined by the amplitude ramp rate (arr) register controlled by an external pin (osk). manual mode allows the user to directly control the output amplitude by writing the scale factor value into the amplitude scale factor (asf) register.
ad9952 rev. b | page 19 of 28 the shaped on-off keying function can be bypassed (disabled) by clearing the osk enable bit (cfr1 [25] = 0). the modes are controlled by two bits located in the most significant byte of the control function register (cfr). cfr1 [25] is the shaped on-off keying enable bit. when cfr1 [25] is set, the output scaling function is enabled and cfr1 [25] bypasses the function. cfr1 [24] is the internal shaped on-off keying active bit. when cfr1 [24] is set, internal shaped on-off keying mode is active; when cfr1 [24] is cleared, external shaped on-off keying mode is active. cfr1 [24] is a dont care if the shaped on-off keying enable bit (cfr1 [25]) is cleared. the power-up condition of the shaped on-off keying is disabled (cfr1 [25] = 0). figure 23 shows the block diagram of the osk circuitry. auto shaped on-off keying mode operation the auto shaped on-off keying mode is active when cfr1 [25] and cfr1 [24] are set. when auto shaped on-off keying mode is enabled, a single-scale factor is internally generated and applied to the multiplier input for scaling the output of the dds core block (see figure 23). the scale factor is the output of a 14-bit counter that increments/decrements at a rate determined by the contents of the 8-bit output ramp rate register. the scale factor increases if the osk pin is high and decreases if the osk pin is low. the scale factor is an unsigned value such that all 0s multiply the dds core output by 0 (decimal) and 0x3fff multiplies the dds core output by 16,383 (decimal). to use the full amplitude (14-bits) with fast ramp rates, the internally generated scale factor step size is controlled via the asf [15:14]. table 6 describes the increment/decrement step size of the internally generated scale factor per the asf [15:14]. a special feature of this mode is that the maximum output amplitude allowed is limited by the contents of the amplitude scale factor register. this allows the user to ramp to a value less than full scale. table 6. auto scale factor internal step size asf [15:14] (binary) increment/decrement size 00 1 01 2 10 4 11 8 osk ramp rate timer the osk ramp rate timer is a loadable down counter that generates the clock signal to the 14-bit counter, which, in turn, generates the internal scale factor. the ramp rate timer is loaded with the value of the asfr every time the counter reaches 1 (decimal). this load and countdown operation continues for as long as the timer is enabled, unless the timer is forced to load before reaching a count of 1. if the load osk timer bit (cfr1 [26]) is set, the ramp rate timer is loaded upon an i/o update or upon reaching a value of 1. the ramp timer can be loaded before reaching a count of 1 by three methods. the first method of loading is by changing the osk input pin. when the osk input pin changes state, the asfr value is loaded into the ramp rate timer, which then proceeds to count down as normal. the second method in which the sweep ramp rate timer can be loaded before reaching a count of 1 is if the load osk timer bit (cfr1 [26]) is set and an i/o update is issued. the last method in which the sweep ramp rate timer can be loaded before reaching a count of 1 is when going from the inactive auto shaped on-off keying mode to the active auto shaped on-off keying mode; that is, when the sweep enable bit is being set. osk pin load osk timer cfr1[26] sync_clk auto desk enable cfr1[24] to dac auto scale factor generator ramp rate timer clock dds core osk enable cfr[25] amplitude scale factor register (asf) 0 0 1 01 01 hold inc/dec enable out cos(x) amplitude ramp rate register (asf) up/dn data load en 03358-023 figure 23. on-off shaped keying, block diagram
ad9952 rev. b | page 20 of 28 ext ernal shaped on - off keying mode operation the external shaped on - off keying mode is enabled by writing cfr1 [ 25 ] to a logic 1 and writing cfr1 [ 24 ] to a logic 0. when configured for external shaped on - off keying, the co n tent of the asfr becomes the scale factor for the data path. the scale factors are synchronized to sync_clk via the i/o u p date functionality. synchronizing multip le ad9952 s the ad9952 product allows easy synchronization of multiple ad9952s. there are three modes of synchronization available to the user: an automatic synchronization mode, a software controlled manual synchronization mode, and a hardware controlled manual synchron i zation mode. in all cases, to synchronize two or more devices, the following considera tions must be observed. first, all units must share a co m mon clock source. trace lengths and path impedance of the clock tree must be designed to keep the phase delay of the di f ferent clock branches as closely matched as possible. second, the i/o update si gnals rising edge must be provided sy n chronously to all devices in the system. finally, regardless of the i n ternal synchronization method used, the dvdd_i/o supply should be set to 3.3 v for all devices that are to be synchronized. avdd and dvdd should be left at 1.8 v. in automatic synchronization mode, one device is chose n as a master; the other device s are slaved to this master. when configured in this mode, the slaves automatically synchr o nize their internal clocks to the sync_clk output signal of the master device. to enter automatic synchronization mode, set the slave devices automatic synchronization bit (cfr1 [ 23 ] = 1). connect the sync_in input(s) to the master sync_clk output. the slave device continuously update s the phase rel a tionship of its s ync_clk until it is in phase with the sync_in input, which is the sync_clk of the master device. when attempting to synchronize devices running at sysclk speeds b e yond 250 msps, the high speed sync enhancement enable bit should be set (cfr2 [ 11 ] = 1). in software manual synchronization mode, the user forces the device to advance the sync_clk rising edge one sysclk cycle ( ? sync_clk period). to activate the manual sy n chronization mode, set the slave devices software manual synchron i zation bit (cfr1 [ 22] = 1). the bit (cfr1 [ 22] ) is cleared immediately. to advance the rising edge of the sync_clk mult i ple times, this bit need s to be set multiple times. in hardware manual synchronization mode, the sync_in i n put pin is configured such that it advance s the risi ng edge of the sync_clk signal each time the device detects a rising edge on the sync_in pin. to put the device into har d ware manual synchroniz a tion mode, set the hardware manual synchronization bit (cfr2 [ 10 ] = 1). unlike the software ma n ual synchronizati on bit, this bit does not self - clear. once the har d ware manual synchronization mode is enabled, all rising edges detected on the sync_in input cause the device to advance the rising edge of the sync_clk by one sysclk c y cle until this enable bit is cleare d (cfr2 [ 10 ] = 0). using a single crystal to drive multiple ad9952 clock inputs the ad9952 crystal oscillator output signal is available on the crystal out pin, enabling one crystal to drive multiple ad9952s. t o drive multiple ad9952s with one crystal, the crystal out pin of the ad9952 using the external cry s tal should be connected to the refclk input of the other ad9952 . the crystal out pin is static until the cfr2 [ 9 ] bit is set, en a bling the output. the drive strength of the crystal out pin is typ i cally very low, so this signal should be buffered prior to using it to drive any loads. serial port operatio n the operations of the ad9952 are controlled by setup data and parameters loaded into the device by means of a serial i/o port. the internal control stru cture is organized as a series of registers. each register is double - buffered. new data is first stored in i/o buffers as it is received. subsequently, the data is transferred to the internal registers that actually control the device o peration. while the i/o buffers are receiving new data , the old data that is already in the control registers continue s to be used until the i/o buffers are transferred into the control registers. the transfer from i/o buffer to control registers requires an i/o update event. this event is triggered by sending a pulse t o the i/o update pin. step 1 : writing data t hrough the serial i/o port to the i/o buffer s there are two phases to a serial i/o communication cycle: ? phase 1: instruction (one byte) ? phase 2: data (one or more byte s) phase 1 is the instruction byte, clocked in by the first eight rising edges of sclk. this single byte provides the ad9952 serial port controller with the information that it needs regarding the upcoming data phase, phase 2. this information tells the se rial port controller whether the data is a read or a write operation, as well as the address of the intended register. once the controller knows the register address, the number of bytes of data to be expected is calculated automatically . t he number of byt es transferred du r ing phase 2 depends on the particular register being accessed. for example, when the co n trol function register 2 is accessed , the data consists of three bytes (or 24 bits) . h owever, if the f r e quenc y tuning w ord 0 register is accessed , the data is four bytes (or 32 bits) . step 1 is complete when both the instruction byte and the required number of data bytes are written to or read from .
ad9952 rev. b | page 21 of 28 after the completion of phase 2 , the ad9952 serial port controller expect s the next eight sclk rising ed ges to be a new instruction byte, followed by an appropriate number of data bytes. see the example operation section of this document for details. all data written into the serial port is clocked into the i/o buffer on the rising edge of sclk. all data read back from the serial port is clocked out on the falling edge of sclk. n ote that the readback operation reads data from registers, not the i/o buffers. if new data has been written to an i/o buffer, but an i/o u pdate has not occu rred, the old data stored in the register is read back ( see step 2: transfer of i/o buffers to registers ) . also, the serial i/o port speed of 25 mb ps refers solely to the speed of sclk during a write operation. as the ad9952 does not generate data, the readback operation is considered a debug feature and is not supported beyond 1 mb ps . instruction byte details the instruction byte con tains the following information. (msb) (lsb) d7 d6 d5 d4 d3 d2 d1 d0 r/ w x x a5 a4 a3 a2 a1 r/ w step 2: transfer of i/o buffers to registers bit 7 of the instruction byte determines whether a read or write data transfer occur s after the instruction byte write. logic high indicates a read operation; a logic 0 indicates a write operation. x, x bit 6 a nd bit 5 , respectively, of the instruction byte are d ont c are. a 5 , a 4 , a 3 , a 2 , a 1 bit 4, bit 3, bit 2, bit 1, and bit 0 , respectively, of the instruction byte determine which register is accessed during the data transfer po r tion of the communication cycle . when the desired setup data is written via the serial port to the i/o buffers, the registers must be updated by issuing an i/o update signal on the i/o u pdate pin. the i/o update signal co nsists of a logic hi gh pulse ( dvdd_i/o) on the i/o update pin. as shown in figure 24 , the i/o u pdate pulse is sampled synchronously by the ad9952 on the rising edge of sync_clk. therefore, the i/o u pdate pulse needs to be set up to the rising edg e of the sync_clk signal. dvdd i/o = 3.3v 4ns 1.8v 6ns dvdd i/o = i/o upd a te t o sync_clk setu p time = tsu sync_clk i/o upd a te 03358-025 figure 24 . setup time for i/o update pulse for s ynchronous d ata t ransfer t o transfer data without having to monitor the sync_clk signal and without having to guarantee setup time, an alternate method is to provide an i/o u pdate pulse for more than one sync_clk period (more than four sysclk periods) asynchronously . if this is done, the i/o u pdate pulse overlap s with at least one sync_clk rising edge. ho wever, there is no guarantee of which sync _clk rising edge transfer s the i/o buffer data to the registers. this method introduces an ambiguity of one sync_clk cycle (four sysclk cycles) in the calculation of the propagation delay and should be avoided if propagation delay of data transfers is an important co nsideration. this method is shown in figure 25. sync_clk i/o upd a te i/o upd a te high pulse gre a ter than 1 sync_clk period 03358-026 figure 25 . i/o update p ulse in a synchronous d ata t ransfer it should be noted that the exact transfer of data from the i/o buffers to the registers actual ly occurs one sync_clk c ycle after the i/o u pdate signal is detected by the ad9952, as shown in figure 26.
ad9952 rev. b | page 22 of 28 sysclk sync_clk i/o update data in i/o buffers data in registers ab ab data 1 data 2 data 3 data 0 data 1 data 2 the device registers an i/o update at point a. the data is transferred from the i/o buffers at point b. 03358-031 figure 26. timing of i/o update si gnal vs. actual register update serial interface port pin description sclkserial clock. the serial clock pin is used to synchronize data to and from the ad9952 and to run the internal state machines. sclk maximum frequency is 25 mhz. cs chip select bar. cs is active low input that allows more than one device on the same serial communication line. the sdo pin and sdio pin go to a high impedance state when this input is high. if driven high during any communication cycle, the cycle is suspended until cs is reactivated low. chip select can be tied low in systems that maintain control of sclk. when toggling cs , it is important that care is taken to meet the clock setup time with respect to the falling edge of cs and tcsu (see figure 27). sdioserial data i/o. data is always written into the ad9952 on this pin. however, this pin can be used as a bidirectional data line. bit 9 of register 0x00 controls the configuration of this pin. the default is logic 0, which configures the sdio pin as bidirectional. in order to guarantee proper serial i/o port operation (see figure 27), data on this pin must be set up and held to the rising edge of sclk on read operations. sdoserial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9952 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. iosyncsynchronizes the i/o port state machines without affecting the registers contents. an active high input on the iosync pin causes the current communication cycle to abort. after iosync returns low (logic 0), another communication cycle can begin, starting with the instruction byte write. scl k sdio cs tcsu tdsu tdh tdh dvdd i/o = 3.3v tcsu = 3ns tdsu = 3ns tdh = 0ns dvdd i/o = 1.8v tcsu = 5ns tdsu = 5ns tdh = 0ns 03358-032 figure 27. serial port i/o setup (tcsu, tdsu) and hold (tdh) times tdv = 25ns s cl k sdio sdo 03358-033 figure 28. serial port i/o data valid time (tdv) during readback msb/lsb transfers the ad9952 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. the control register, register 0x00, bit 8, controls this functionality. the default value of register 0x00 [8] is low (msb first). when the control register (0x00 [8]) is set high, the ad9952 serial port is in lsb-first format. the instruction byte must be written in the format indicated by the control register (0x00 [8]), and the instruction byte must be written from least significant bit to most significant bit (right to left in the table located in the instruction byte details section). note that even in lsb-first mode, the two respective phases of the communication cycle, the instruction byte phase and the data communication phase, retain their respective positions.
ad9952 rev. b | page 23 of 28 when in lsb - f irst mode, the device read s the i nstruction b yte first (lsb to msb), then calculate s the expected number of bytes from the address provided, and then receive s /provide s data from the referenced registe r in lsb - first format (lsb to msb of the register selected). example operation in this example, the amplitude scale factor is calculated and written to present a 45 phase offset on the output of the ad9952. first, the default msb - first case is considered. then, the alternate lsb - first method is presented. for the purpose of the example, the following assumptions are made: ? t he microcontroller is currently meeting the setup and hold times for the s erial i/o port (th is is a software only example) . ? t he phase offset change needs to occur at a known point in time (the data tr ansfer needs to be synchronous) . ? n o other values are written or altered during the example. msb - first mode (default) case first, the p hase o ffset word (pow) needs to be calculated. per the formula in the phase offset word (pow) section, the pow is calculated to be 45/360 2 14 or 2048 (h 800). next, the instruction byte to write to the pow needs to be sent. the first bit is 0, to indicate a write. the next two bits are dont care bits , and are set to 0 . the last 5 bits correspond to the pow address, which is h05. this makes the instruction byte: b00001001. next, the data calculated in step 1 is sent to the part. the pow is 2 bytes wide. to make the 14 - bit value fit into the 16 - bit register, the 2 msbs are padded with dont care bits . in this example, the dont care bits ar e assumed to be 0 . the 2 data bytes therefore are b00 001000 00000000. once the 24 bits of data are sent to the part (8 bits of instruction byte a nd 16 bits of data), the p hase o ffset w ord i/o b uffer is changed, but the change has not been made in the p hase o ffset word (pow) register. as no other data is being written in this example, the i/o update pulse , which is 1.5 sync_clk cycles in duration , i s sent to the i/o u pdate pin. this transfers the data from the pow i/o b uffer to the pow register. lsb first mode case the values calculated in the msb - first mode case are s till valid. the order of the bits in the instruction byte and in the data bytes for the pow need to be reversed. first, the instruction byte is sent. because the part is now in lsb - first mode, the value sent is b10010000. next, the data bytes are sent in lsb - first mode: b00000000 00010000. finally, as before, the i/o u pdate pin is puls ed with a high signal for duration of 1.5 sync_clk cycles, to transfer the contents of the pow i/o b uffer to the pow register. power - down functions the ad9952 supports an externally controlled or hardware power - down feature as well as the more common softw are pr o grammable power - down features found in other analog devices dds pro d ucts. the software control power - down allows the dac, comparator, pll, input clock circuitry, and digital logic to be individually powered down via unique control bits (cfr1 [ 7:4 ] ) . with the exception of cfr1 [ 6 ] , these bits are not active when the exte r nally controlled power - down pin (pwrdwnctl) is high. exte r nal power - down control is supported on the ad9952 via the pwrdwnctl input pin. when the pwrdwnctl input pin is high, the ad 9952 enter s a power - down mode based on the cfr1 [ 3 ] bit. when the pwrdwnctl input pin is low, the exte r nal power - down control is inactive. when the cfr1 [ 3 ] bit is 0 and the pwrdwnctl input pin is high, the ad9952 is put into a fast recovery power - down mo de. in this mode, the digital logic and the dac digital logic are powered down. the dac bias circuitry, comparator, pll, oscillator, and clock input circuitry is not powered down. the comparator can be individually powered down by setting the co m parator po wer - down bit, cfr1 [ 6 ] = 1. when the cfr1 [ 3 ] bit is high, and the pwrdwnctl input pin is high, the ad9952 is put into the full power - down mode. in this mode, all functions are powered down. this includes the dac and pll, which take a significant amount of time to power up. when the pwrdwnctl input pin is high, the individual power - down bits (cfr1 [ 7 ] and cfr1 [ 5:4 ] ) are invalid ( d ont c are) and unused. when the pwrdwnctl input pin is low, the individual power - down bits control the power - down modes of oper a tion. note that the power - down signals are all designed such that a logic 1 indicates the low power mode and a logic 0 ind i cates the active or power - up mode. table 7 indicates the logic level for each power - down bit that drives o ut of the ad9952 core logic to the analog se c tion and the digital clock generation section of the chip for the external power - down operation.
ad9952 rev. b | page 24 of 28 table 7 . power - down control functions control mode active description pwrdwnctl = 0 c fr1 [ 3 ] d ont c are software c ontrol digital p ower - d own = cfr1 [ 7 ] comparator p ower - d own = cfr1 [ 6 ] dac power - d own = cfr1 [ 5 ] input c lock p ower - d own = cfr1 [ 4 ] pwrdwnctl = 1 cfr1 [ 3 ] = 0 external c ontrol, f ast r ecovery p ower - d own m ode digital power - d own = 1b1 comparator p ower - d own = 1b0 or cfr1 [ 6 ] dac power - d own = 1b0 input c lock p ower - d own = 1b0 pwrdwnctl = 1 cfr1 [ 3 ] = 1 external c ontrol, f ull p ower - d own m ode digital power - d own = 1b1 comparator p ower - d own = 1b1 dac power - d own = 1b1 input c lock p ower - d own = 1b1
ad9952 rev. b | page 25 of 28 layout consideration s for the best performance, the following layout guidelines should be observed. always provide the analog power supply (avdd) and the digital power supply (dvdd) on separate supplies, even if just from two differe nt voltage regulators driven by a common supply. likewise, the ground connections (agnd, dgnd) should be kept separate as far back to the source as possible (for example, separate the ground planes on a loca l ized board, even if the grounds connect to a com mon point in the system). bypass capacitors should be placed as close to the supply pin as possible. usually, a multitiered bypassing scheme consisting of a small high frequency capacitor (100 pf) placed c lose to the supply pin and progressively larger cap acitors (0.1 f, 10 f) placed fu r ther away from the actual supply source works best .
ad9952 rev. b | page 26 of 28 suggested application circuits lpf ad9952 refclk rf/if input modul a ted/ demodulated signal 03358-027 figure 29. synchronized lo for upconversion/down conversion filter phase comparator loop filter ad9952 tuning word ref s ign a l vco 03358-028 figure 30. digitally programmable divide-by-n function in pll tuning word cmos level clock ad9952 dds ad9952 on-chip comparator iout iout lpf lpf 03358-029 figure 31. frequency agile clock generator crystal frequency tuning word phase offset word 2 i/i-bar baseband frequency tuning word phase offset word 1 q/q-bar baseband sync in ad9952 dds refclk refclk refclk lpf sync out crystal out ad9952 dds iout iout lpf iout iout rf out 03358-030 figure 32. two ad9952s synchronized to provide i carriers and q carriers with independent phase offsets for nulling
ad9952 rev. b | page 27 of 28 o utline dimensions for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant t o jedec s t andards ms-026-abc 0.50 bsc lead pitch 0.27 0.22 0.17 9.00 bsc sq 7.00 bsc sq 37 37 48 48 1 13 12 1 12 24 13 24 25 36 25 36 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarit y view a ro ta ted 90 ccw se a ting plane 0 min 7 3.5 0 0.15 0.05 0.75 0.60 0.45 1.20 max view a t op view (pins down) bot t om view (pins up) pin 1 3.50 sq exposed p ad 011708-a figure 33 . 48 - lead thin quad flat package, exposed pad [tqfp _ ep] (sv - 48 - 4) dimensions shown in millimeters ordering guide model temperature range package description ordering quantity package option ad9952ysv C 40c to +105c 48- lead thin quad flat package, exposed pad [tqfp_ep] sv -48-4 ad9952ysv - reel7 C 40c to +105c 48- lead thin quad flat package, exposed pad [tqfp_ep] 500 sv -48-4 AD9952YSVZ 1 C 40c to +105c 48- lead thin quad flat package, exposed pad [tqf p_ep] sv -48-4 AD9952YSVZ - reel7 1 C 40c to +105c 48- lead thin quad flat package, exposed pad [tqfp_ep] 500 sv -48-4 ad9954 /pcb z 1 evaluation board used for the ad9952 1 z = rohs compliant part.
ad9952 rev. b | page 28 of 28 notes ? 2003 C 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03358 - 0 - 5/09(b)

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